1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ1032

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Q1032DVMetaASIC interview problem

Ready-valid protocol assertions

TechniquesDVSystemVerilog assertionsReady-validBackpressure

DifficultyMedium

TopicAssertions and Formal

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A monitor must catch a producer that changes or withdraws an item while the consumer applies backpressure. Write clocked SVA properties for the stated ready-valid rules and one useful coverage sequence.

Starting declarationSystemVerilog

input logic clk, rst_n, valid, ready;
input logic [31:0] data;

Example input and output

Use this case to check your interpretation

Input

Cycle 1: valid=1 ready=0 data=32'hAA
Cycle 2: valid=1 ready=0 data=32'hAA
Cycle 3: valid=1 ready=1 data=32'hAA

Output

All assertions pass; the two-stalls-then-transfer cover property is hit.

Explanation

The producer holds both valid and payload across every stalled edge, then completes the transfer without any X or Z values.

Requirements (4)

Disable every assertion while rst_n is 0.
If valid is 1 and ready is 0 on one edge, require valid to remain 1 and data to be stable on the next edge.
On every rising edge while reset is inactive, assert that valid is not X or Z. If valid is exactly 1, also assert that every bit of data is known.
Cover a legal sequence with two stalled cycles followed by a cycle on which valid and ready are both 1.