DescriptionQ891
Q891DVDesignASIC interview problem
Procedural delays
TechniquesSystemVerilogBasic scheduling
DifficultyEasy
TopicSV
LanguageSystemVerilog
Format4 choices
01
Problem
Assuming the time unit is 1 ns, at what simulation times are x assigned 1 and 2?
Starting declarationSystemVerilog
int x;
initial begin
x = 0;
#5 x = 1;
#3 x = 2;
end02