DescriptionQ863
Q863DesignASIC interview problem
Detect nonoverlapping 10110 sequences
TechniquesDesignSystemVerilogFSMSequence detectorNonoverlap
DifficultyMedium
TopicSequential RTL
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Design a serial sequence detector that accepts one bit per clock and emits a one-cycle pulse when 10110 completes. Bits consumed by a match cannot begin the next match.
Starting declarationSystemVerilog
input logic clk, rst_n, bit_in;
output logic detected;Example input and output
Use this case to check your interpretationInput
bit_in at successive rising edges = 1, 0, 1, 1, 0Output
detected = 0, 0, 0, 0, 1Explanation
The fifth sampled bit completes 10110, so the registered output pulses for the following cycle and the FSM returns to its no-prefix state.
02
Requirements (4)
- Recognize the exact five-bit pattern 10110 without overlap.
- Pulse detected for exactly one destination clock cycle.
- Clear all partial-match state on reset.
- Retain the longest useful suffix after every mismatch, but return to the start state after a full match.