DescriptionQ782
Q782DesignASIC interview problem
Compute serial two's complement LSB first
TechniquesTwo's complementSerial arithmeticMealy FSMBit stream
DifficultyMedium
TopicFSMs
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Build a synchronous serial two's-complementer for words arriving least-significant bit first. Copy bits through the first 1 inclusive, invert all later bits, and produce a combinational result for each valid input bit.
Example input and output
Use this case to check your interpretationInput
start with 4-bit word arriving LSB-first as [0,0,1,1]Output
two's-complement output bits=[0,0,1,0]Explanation
Zeros are copied through the first accepted one inclusive, then the later high bit is inverted; invalid gaps hold the seen-one state.
02
Requirements (4)
- start marks the first valid bit of a new word and clears prior history.
- Hold state when valid_in is low and drive data_out to zero while invalid.
- The first 1 passes unchanged; only following valid bits are inverted.
- Explain why an unknown-length MSB-first stream cannot satisfy the same zero-buffering contract.