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Hardware interview practice

Compute serial two's complement LSB first

MediumFSMsSystemVerilog

Build a synchronous serial two's-complementer for words arriving least-significant bit first. Copy bits through the first 1 inclusive, invert all later bits, and produce a combinational result for each valid input bit.

Try it in the question bankReason first. Then compare.

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Reviewed example

Work through one case

Input
start with 4-bit word arriving LSB-first as [0,0,1,1]
Expected output
two's-complement output bits=[0,0,1,0]

Zeros are copied through the first accepted one inclusive, then the later high bit is inverted; invalid gaps hold the seen-one state.

What to cover

Requirements

  1. start marks the first valid bit of a new word and clears prior history.
  2. Hold state when valid_in is low and drive data_out to zero while invalid.
  3. The first 1 passes unchanged; only following valid bits are inverted.
  4. Explain why an unknown-length MSB-first stream cannot satisfy the same zero-buffering contract.
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