1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ743

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Q743DesignQualcommASIC interview problem

Derive min and max input/output delay constraints

TechniquesDesignConstraintsSDCClocking

DifficultyHard

TopicTiming

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A virtual clock v_if represents the external device clock at the chip reference with no clock-board skew. Input device Tco is 0.2..1.2 ns and input-board data delay is 0.3..0.8 ns. For output, receiver setup=0.7 ns, hold=0.2 ns, and output-board data delay is 0.1..0.6 ns. Write the four SDC delays and show their derivation.

Starting declarationSystemVerilog

input port din relative to virtual clock v_if
output port dout relative to virtual clock v_if
input: Tco_min=0.2,Tco_max=1.2,board_min=0.3,board_max=0.8 ns
output: Tsetup=0.7,Thold=0.2,board_min=0.1,board_max=0.6 ns
use Synopsys-style set_input_delay/set_output_delay

Example input and output

Use this case to check your interpretation

Input

Case 1: Scenario: `set_input_delay -clock v_if -max 2.0 [get_ports din]` and `-min 0.5` encode the input window.
Case 2: `set_output_delay -clock v_if -max 1.3 [get_ports dout]`
Case 3: `set_output_delay -clock v_if -min -0.1 [get_ports dout]`

Output

Case 1: Expected behavior: `set_input_delay -clock v_if -max 2.0 [get_ports din]` and `-min 0.5` encode the input window.
Case 2: Encodes the receiver setup plus worst board delay.
Case 3: Encodes 0.1 ns board minimum minus 0.2 ns receiver hold.

Explanation

The shown result follows by applying this rule: Draw the external launch/capture timing budget before converting each min/max sum into SDC. The cases also demonstrate this requirement: Use both -min and -max commands relative to v_if and explain that omitting either leaves one interface timing side unconstrained.

Requirements (4)

Set input max to Tco_max+board_max=2.0 ns and input min to Tco_min+board_min=0.5 ns.
Set output max to receiver setup+board_max=1.3 ns.
Set output min to board_min-receiver hold=-0.1 ns under the stated common reference-clock convention.
Use both -min and -max commands relative to v_if and explain that omitting either leaves one interface timing side unconstrained.