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DescriptionQ835
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Q835DesignQualcommASIC interview problem

Constrain aligned transactions inside one page

TechniquesDesignSystemVerilogConstraintsDDR
DifficultyMedium
TopicProtocols and Interfaces
LanguageSystemVerilog
Requirements4 checkpoints
01

Problem

A transaction uses a 48-bit address and a byte length of 1, 2, 4, or 8. The entire access must remain in 0x1000 through 0x1FFF. Write SystemVerilog constraints for legal length, alignment, and range.

Starting declarationSystemVerilog
rand bit [47:0] addr
rand int unsigned length
legal page: 48'h1000..48'h1FFF

Example input and output

Use this case to check your interpretation
Input
Case 1: addr=48'h1000, length=8
Case 2: addr=48'h1004, length=8
Case 3: addr=48'h1FFC, length=8
Output
Case 1: Is legal.
Case 2: Is illegal because it is misaligned.
Case 3: Is illegal because it crosses the page end.
Explanation

The shown result follows by applying this rule: The legal length set is exact. The cases also demonstrate this requirement: Constrain addr + length - 1 <= 48'h1FFF using widened arithmetic so overflow cannot wrap.

02

Requirements (4)

  • Constrain length inside {1,2,4,8}.
  • Constrain addr >= 48'h1000 and addr <= 48'h1FFF.
  • Constrain addr % length == 0.
  • Constrain addr + length - 1 <= 48'h1FFF using widened arithmetic so overflow cannot wrap.