1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ722

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Q722DesignMetaASIC interview problem

Four-requester round-robin arbiter

TechniquesDesignSystemVerilogArbiterRound robin

DifficultyMedium

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Four clients share a one-cycle service slot. Design a synthesizable combinational round-robin grant and sequential priority pointer with deterministic reset and idle behavior.

Starting declarationSystemVerilog

input logic clk, rst_n;
input logic [3:0] req;
output logic [3:0] grant;

Example input and output

Use this case to check your interpretation

Input

After reset, req=4'b0101 for two cycles

Output

First grant=0001; next grant=0100

Explanation

The pointer starts at requester 0 and then advances to requester 1 after the first grant.

Requirements (4)

grant is combinational, one-hot-or-zero, and selects the first asserted requester encountered from the current priority pointer with wraparound.
On a rising edge with a nonzero grant, move the pointer to the requester immediately after the granted one.
If req is zero, drive grant zero and leave the pointer unchanged.
Whenever rst_n is 0, drive grant=0; on a rising edge with rst_n=0, set requester 0 as the first priority.