1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ503

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Q503DesignDVASIC interview problem

Arbitrate fairly between two requesters

TechniquesRound robinFairnessOne-hot grantBFM

DifficultyMedium

TopicArbiters

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design a two-requester round-robin arbiter and a requester BFM. When both requests remain asserted, grants must alternate; when only one requests, it may be granted every cycle.

Example input and output

Use this case to check your interpretation

Input

req0=req1=1 for four completed service cycles; reset priority starts at requester 0

Output

grants=01,10,01,10

Explanation

Both active requesters alternate, and priority rotates only after each grant is sampled as completed service.

Requirements (4)

Produce at most one grant per cycle and never grant an inactive requester.
Update priority only after a grant represents a completed unit of service.
A continuously asserted requester must not starve.
The BFM must hold request until its grant is sampled, then release it cleanly.