1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ225

Q225DesignDVNVIDIAASIC interview problem

Design and verify a round-robin arbiter

TechniquesDesignDVArbiterFairnessAssertions

DifficultyHard

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Design a four-request round-robin arbiter with one-cycle one-hot grants and verification for safety and bounded fairness.

Starting declarationSystemVerilog

input logic clk, rst_n;
input logic [3:0] req;
output logic [3:0] gnt;

Use this case to check your interpretation

Input

Last grant was requester 1; req[1] and req[3] remain high

Output

Next grant is requester 3; the following successful arbitration grants requester 1

Explanation

Scanning starts at 2 after grant 1, so requester 3 is encountered before requester 1.

Grant at most one asserted request.
After granting i, begin the next scan at i+1 modulo four.
When no request is active, grant zero and preserve the priority pointer.
Prove a continuously asserted request is served within four successful arbitration cycles.