DescriptionQ617
Q617DesignMetaASIC interview problem
Eight-entry asynchronous FIFO
TechniquesDesignCDCAsync FIFOGray codeReset
DifficultyMedium
TopicClock Domain Crossing
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A 32-bit producer and consumer use unrelated clocks. Implement an eight-entry asynchronous FIFO with local full/empty flags, Gray-pointer crossings, and reset-release gating in both domains.
Starting declarationSystemVerilog
input logic wclk, wrst_n, wvalid;
output logic wready;
input logic [31:0] wdata;
input logic rclk, rrst_n, rready;
output logic rvalid;
output logic [31:0] rdata;Example input and output
Use this case to check your interpretationInput
After reset, write A once and hold rready=1Output
rvalid eventually rises and the first accepted read returns AExplanation
The write Gray pointer crosses two rclk stages before rempty clears; the data bus remains in dual-port memory and FIFO order is preserved.
02
Requirements (4)
- Use 4-bit binary read and write pointers for eight entries, convert each next pointer to Gray code, and synchronize only Gray pointers through two flops into the opposite domain.
- Accept a write only on wvalid and wready; assert local full when the next write Gray pointer equals the synchronized read Gray pointer with its two most-significant bits inverted.
- Accept a read only on rvalid and rready; assert local empty when the next read Gray pointer equals the synchronized write Gray pointer, and preserve FIFO order.
- For initialization or flush, assert both resets together; each local reset clears its binary pointer, Gray pointer, and flag, and permit no traffic until both resets have been released and synchronized.