1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ891

Q891DesignDVNVIDIAASIC interview problem

Implement asynchronous FIFO full and empty logic

TechniquesDesignDVCDCAsynchronous FIFOGray code

DifficultyHard

TopicClock Domain Crossing

LanguageSystemVerilog

Requirements4 checkpoints

Design the pointer, synchronization, memory, full, empty, and coordinated-reset behavior for a depth-16 dual-clock FIFO.

Starting declarationSystemVerilog

// write: wclk, wrst_n, w_en, wdata, w_full
// read:  rclk, rrst_n, r_en, rdata, r_empty

Use this case to check your interpretation

Input

Sixteen accepted writes and no reads

Output

w_full asserts after the sixteenth pointer advance

Explanation

The next write Gray pointer reaches the state one buffer length ahead of synchronized read Gray.

Use 5-bit binary/Gray pointers with a 4-bit memory address.
Register local Gray pointers and synchronize each Gray bus through two destination flops.
Register empty from next read Gray equaling synchronized write Gray; register full from next write Gray equaling synchronized read Gray with its top two bits inverted.
Treat reset as a coordinated flush and block both sides until both domains observe synchronized release.