DescriptionQ611
Q611DesignAppleASIC interview problem
Rank crosstalk delay for three adjacent wires
TechniquesDesignPhysical designSignal integrityCrosstalkMiller effect
DifficultyMedium
TopicTiming
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A victim wire switches from 0 to 1 while two equally coupled neighbors switch in the same time window. Rank victim delay when both neighbors switch 0-to-1, remain quiet, or switch 1-to-0.
Example input and output
Use this case to check your interpretationInput
victim 0->1; case S: neighbors 0->1; case Q: neighbors static; case O: neighbors 1->0Output
fastest S, then Q, slowest OExplanation
Same-direction switching minimizes voltage change across the coupling capacitors, while opposite switching creates roughly twice the voltage excursion and the largest effective load.
02
Requirements (4)
- Assume equal coupling, aligned transitions, linear drivers, and otherwise identical loading.
- Give a fastest-to-slowest ranking for same-direction, quiet-neighbor, and opposite-direction cases.
- Explain the voltage change across each coupling capacitor and the corresponding effective load.
- Name at least two applicable mitigations such as spacing, shielding, layer change, stronger drive, or transition separation.