1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

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Q728DesignIntelASIC interview problem

Choose an optimum repeater count

TechniquesDesignPhysical design

DifficultyMedium

TopicTiming

LanguageSystemVerilog

Requirements4 checkpoints

Problem

An unbuffered wire has 800 ps delay. Splitting it into n equal segments gives total wire delay 800/n ps, and each of n−1 repeaters adds 80 ps. Use integer n from 1 through 8. Write the delay calculation and choose the minimum-delay design.

Starting declarationSystemVerilog

D(n) = 800/n + 80(n-1) ps
integer n in 1..8
repeaters = n-1

Example input and output

Use this case to check your interpretation

Input

Case 1: n=2
Case 2: n=3
Case 3: n=4

Output

Case 1: D = 400 + 80 = 480 ps.
Case 2: D ≈ 266.7 + 160 = 426.7 ps.
Case 3: D = 200 + 240 = 440 ps.

Explanation

The shown result follows by applying this rule: The answer distinguishes segments from repeaters. The cases also demonstrate this requirement: Show that neighboring n=2 gives 480 ps and n=4 gives 440 ps.

Requirements (4)

Evaluate the stated formula for every integer n from 1 through 8 or prove the discrete minimum around the continuous optimum.
Report n=3 segments and two repeaters.
Report D(3) = 800/3 + 160 ≈ 426.7 ps.
Show that neighboring n=2 gives 480 ps and n=4 gives 440 ps.