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Hardware interview practice

Rank crosstalk delay for three adjacent wires

MediumTimingSystemVerilog

A victim wire switches from 0 to 1 while two equally coupled neighbors switch in the same time window. Rank victim delay when both neighbors switch 0-to-1, remain quiet, or switch 1-to-0.

Reviewed example

Work through one case

Input
victim 0->1; case S: neighbors 0->1; case Q: neighbors static; case O: neighbors 1->0
Expected output
fastest S, then Q, slowest O

Same-direction switching minimizes voltage change across the coupling capacitors, while opposite switching creates roughly twice the voltage excursion and the largest effective load.

What to cover

Requirements

  1. Assume equal coupling, aligned transitions, linear drivers, and otherwise identical loading.
  2. Give a fastest-to-slowest ranking for same-direction, quiet-neighbor, and opposite-direction cases.
  3. Explain the voltage change across each coupling capacitor and the corresponding effective load.
  4. Name at least two applicable mitigations such as spacing, shielding, layer change, stronger drive, or transition separation.
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