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DescriptionQ568
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Q568DVMetaASIC interview problem

Nonoverlapped implication timing

TechniquesDVSVAImplicationSampling
DifficultyEasy
TopicAssertions and Formal
LanguageSystemVerilog
Format4 choices
01

Problem

An assertion is sampled on every rising edge and uses the property `a |=> b`. If a is true on cycle 10, when must b be true for that attempt to pass?

02

Answer choices (4)