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Hardware interview practice

Nonoverlapped implication timing

EasyAssertions and FormalSystemVerilog

An assertion is sampled on every rising edge and uses the property `a |=> b`. If a is true on cycle 10, when must b be true for that attempt to pass?

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Answer choices

  1. A. On cycle 11, the next sampled rising edge.
  2. B. On every cycle from 10 onward until a becomes false.
  3. C. At any time before cycle 12, including between clock edges.
  4. D. On cycle 10, the same sampled rising edge.
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