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DescriptionQ449
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Reason for miss-status entries

TechniquesArchitectureCacheMSHRNonblocking cache
DifficultyEasy
TopicComputer Architecture
LanguageSystemVerilog
Format4 choices
01

Problem

A cache should continue serving hits and issue another miss while an earlier line fill is still outstanding. What structure is needed to track those unfinished misses?

02

Answer choices (4)