DescriptionQ678
Q678ArchNVIDIAASIC interview problem
Recognize write-back cache behavior
TechniquesArchCacheWrite policyMemory traffic
DifficultyEasy
TopicComputer Architecture
LanguageSystemVerilog
Format4 choices
01
Problem
A processor writes one resident cache line ten times. Main memory sees no write until the dirty line is evicted. Which policy is this?
02
