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DescriptionQ678
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Q678ArchNVIDIAASIC interview problem

Recognize write-back cache behavior

TechniquesArchCacheWrite policyMemory traffic
DifficultyEasy
TopicComputer Architecture
LanguageSystemVerilog
Format4 choices
01

Problem

A processor writes one resident cache line ten times. Main memory sees no write until the dirty line is evicted. Which policy is this?

02

Answer choices (4)