DescriptionQ442
Q442DVASIC interview problem
Check ordered grants for overlapping requests
TechniquesProtocol checkerOutstanding queueOrderingLatency
DifficultyHard
TopicTemporal Checks
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Request pulses may overlap. Queue up to eight accepted request IDs and require one ordered grant per request within 1 through 15 clocks.
Starting declarationSystemVerilog
input logic clk, rst_n, req, grant;
input logic [7:0] req_id, grant_id;Example input and output
Use this case to check your interpretationInput
req A at cycle 2, req B at 3, grant A at 5, grant B at 8Output
pass; A retires at latency 3 and B retires at latency 5Explanation
The FIFO binds each grant to one oldest request, preserving order even while requests overlap.
02
Requirements (4)
- Store each accepted request ID and issue cycle.
- Compare each grant only with the queue front; a wrong-ID grant reports an error without retiring that request.
- Flag zero or excessive latency, wrong order, overflow, and unsolicited grants.
- Report and retire a timed-out front request once so later obligations can still be checked; reset clears every pending obligation.