DescriptionQ1014
Q1014DVDesignASIC interview problem
Check a single-outstanding request/grant protocol
TechniquesDVDesignSystemVerilogProtocol checkerLatencySVA
DifficultyMedium
TopicProtocol Verification
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Implement a clocked checker for one-cycle request pulses. Only one request may be pending, and its grant must arrive from 1 through 10 clocks after the request cycle.
Starting declarationSystemVerilog
input logic clk, rst_n, req, grant;
output logic error;Example input and output
Use this case to check your interpretationInput
req pulses at cycle 4; grant pulses at cycle 14Output
pass, with error remaining 0Explanation
Cycle 14 is exactly ten rising edges after the request cycle, so it is the last legal grant cycle under the stated convention.
02
Requirements (4)
- Start counting only when a request is accepted while no request is pending.
- Flag a second request before the outstanding request completes.
- Accept a grant only 1 through 10 clocks after its request and treat an unsolicited grant as an error.
- Make error sticky until reset, and clear pending state, age, and error on reset.