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Hardware interview practice

Check ordered grants for overlapping requests

HardTemporal ChecksSystemVerilog

Request pulses may overlap. Queue up to eight accepted request IDs and require one ordered grant per request within 1 through 15 clocks.

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Starting point

Question code

input logic clk, rst_n, req, grant;
input logic [7:0] req_id, grant_id;
Reviewed example

Work through one case

Input
req A at cycle 2, req B at 3, grant A at 5, grant B at 8
Expected output
pass; A retires at latency 3 and B retires at latency 5

The FIFO binds each grant to one oldest request, preserving order even while requests overlap.

What to cover

Requirements

  1. Store each accepted request ID and issue cycle.
  2. Compare each grant only with the queue front; a wrong-ID grant reports an error without retiring that request.
  3. Flag zero or excessive latency, wrong order, overflow, and unsolicited grants.
  4. Report and retire a timed-out front request once so later obligations can still be checked; reset clears every pending obligation.
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