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DescriptionQ038
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Q038DVASIC interview problem

AXI Write Address Changes While Stalled

TechniquesDVWaveform DebuggingAXI
DifficultyMedium
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. AWVALID and AWADDR are driven by the source, while AWREADY is driven by the receiver. Rule to apply: While AWVALID=1 and AWREADY=0, AWVALID must remain high and AWADDR must remain unchanged until the address handshake. Which channel stability assertion fails first?

Waveform for AXI Write Address Changes While Stalled. Signals: AWVALID, AWREADY, AWADDR. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)