1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ505

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Q505DVIntelASIC interview problem

Verify a four-by-four AXI bridge

TechniquesDVDesignUVMClockingAXI

DifficultyMedium

TopicUVM

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Four AXI masters share a bridge to four slaves. Address selects the slave, and responses may reorder across IDs. Design a UVM environment and test plan for the bridge.

Starting declarationSystemVerilog

4 AXI master-side interfaces
4 AXI slave-side interfaces
address map: one range per slave
ID width: 4 bits
per-slave round robin: a continuous requester is served within 4 accepted address transfers when the target accepts continuously
active-low synchronous reset

Example input and output

Use this case to check your interpretation

Input

Case 1: Master 2, ID 5, address in slave-3 range
Case 2: IDs 1 and 2
Case 3: An unmapped address

Output

Case 1: Must exit slave 3 and return to master 2.
Case 2: May respond in reverse issue order; two ID-1 requests may not.
Case 3: Returns DECERR and creates no slave transfer.

Explanation

The shown result follows by applying this rule: Prediction includes address routing and response return routing. The cases also demonstrate this requirement: Cover every master × slave × response and concurrent requests from all four masters.

Requirements (4)

Use active master agents, passive monitors on both sides, an address predictor, and an ID-aware scoreboard.
Check arbitration, decode errors, reset in flight, and backpressure. Assert that a continuously requesting master is served within four eligible address handshakes whenever the selected slave remains able to accept.
Enforce order within one ID while permitting legal reordering across different IDs.
Cover every master × slave × response and concurrent requests from all four masters.