1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ294

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Q294ArchNVIDIAASIC interview problem

Partition a cache address

TechniquesArchCacheAddressingAssociativity

DifficultyMedium

TopicComputer Architecture

LanguageSystemVerilog

Requirements4 checkpoints

Problem

For a 32 KiB cache with 64-byte lines and 32-bit byte addresses, calculate tag, index, and offset widths for 4-way, direct-mapped, and fully associative organizations.

Starting declarationSystemVerilog

capacity = 32 KiB
line_size = 64 B
address_width = 32 bits

Example input and output

Use this case to check your interpretation

Input

4-way, 32 KiB, 64-byte lines, 32-bit addresses

Output

128 sets; tag=19, index=7, offset=6 bits

Explanation

The cache has 32768/(64*4)=128 sets, requiring seven index bits. Six offset bits select a byte in the line, leaving 32-7-6=19 tag bits.

Requirements (4)

Assume power-of-two dimensions and no virtual-address or sector-cache complications.
Compute offset bits from line size.
Compute index bits from set count, not total line count.
Use the remaining high bits as tag bits and show each set-count calculation.