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Hardware interview practice

Partition a cache address

MediumComputer ArchitectureSystemVerilog

For a 32 KiB cache with 64-byte lines and 32-bit byte addresses, calculate tag, index, and offset widths for 4-way, direct-mapped, and fully associative organizations.

Starting point

Question code

capacity = 32 KiB
line_size = 64 B
address_width = 32 bits
Reviewed example

Work through one case

Input
4-way, 32 KiB, 64-byte lines, 32-bit addresses
Expected output
128 sets; tag=19, index=7, offset=6 bits

The cache has 32768/(64*4)=128 sets, requiring seven index bits. Six offset bits select a byte in the line, leaving 32-7-6=19 tag bits.

What to cover

Requirements

  1. Assume power-of-two dimensions and no virtual-address or sector-cache complications.
  2. Compute offset bits from line size.
  3. Compute index bits from set count, not total line count.
  4. Use the remaining high bits as tag bits and show each set-count calculation.
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