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DescriptionQ254
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Q254DesignGoogleASIC interview problem

Spot an unintended latch

TechniquesDesignSystemVerilogalways_combLatch inference
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Format4 choices
01

Problem

An `always_comb` block assigns `y = a` only when `enable` is 1 and has no assignment to `y` when `enable` is 0. What behavior does this incomplete assignment request?

02

Answer choices (4)