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Hardware interview practice

Spot an unintended latch

EasyRTL DesignSystemVerilog

An `always_comb` block assigns `y = a` only when `enable` is 1 and has no assignment to `y` when `enable` is 0. What behavior does this incomplete assignment request?

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Answer choices

  1. A. SystemVerilog automatically drives `y` to 0 when `enable` is 0, so no storage is needed.
  2. B. `y` becomes high impedance whenever `enable` is 0 because procedural assignments release the signal.
  3. C. `y` must retain its previous value when `enable` is 0, which requires storage and violates the intended combinational behavior.
  4. D. The block infers a flip-flop that updates only on the next positive clock edge.
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