1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ253

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Q253DesignAppleASIC interview problem

Sequence retention, isolation, power switch, and restore

TechniquesDesignLow powerPower sequencingSequencerestore

DifficultyHard

TopicLow Power

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A controller turns one register domain off and later wakes it. External save, power-good, and restore acknowledgements may stall. Implement the synthesizable SystemVerilog power-state controller and its timeout behavior.

Starting declarationSystemVerilog

input logic clk, rst_n, sleep_req, wake_req;
input logic save_ack, pwr_good, restore_ack;
output logic save_req, iso_en, switch_off, restore_req;
output logic ready, error;

Example input and output

Use this case to check your interpretation

Input

sleep_req at C0, save_ack at C2, pwr_good falls at C3, wake_req at C5, pwr_good rises at C7, and restore_ack at C8.

Output

After C8 the controller is ON with ready=1, error=0, and all four control requests deasserted.

Explanation

Each acknowledgement advances the ordered save-isolate-power-wake-restore sequence before isolation is finally removed.

Requirements (4)

Reset enters ON with ready=1, all four control outputs and error=0. In ON, an accepted sleep_req clears ready and asserts save_req until save_ack.
After save_ack, deassert save_req, assert iso_en and switch_off, and wait for pwr_good=0 before entering OFF; wake_req is acted on only in OFF.
On wake_req, deassert switch_off but keep iso_en=1; after pwr_good=1 assert restore_req until restore_ack, then deassert restore_req and iso_en and return to ON with ready=1.
Each wait for save_ack, pwr_good transition, or restore_ack allows four sampled cycles including its entry cycle; timeout enters ERROR with error=1, ready=0, iso_en=1, switch_off=1, other controls=0 until reset.