DescriptionQ997
Q997DesignAMDASIC interview problem
Prove retention across a power cycle
TechniquesDesignLow powerPower sequencingProvecycle
DifficultyHard
TopicLow Power
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A four-bit retained register can be written while powered, saved before shutdown, clamped to zero while off, and restored after power returns. Write SystemVerilog assertions and minimal reference state for the retention protocol.
Starting declarationSystemVerilog
input logic clk,rst_n,power_on,save,restore,wr_en;
input logic [3:0] wr_data,q;Example input and output
Use this case to check your interpretationInput
q is written to 4'hA, save is accepted, power turns off with q clamped to zero, power returns, and restore is accepted.Output
On the following edge q must equal 4'hA and all saved/off/restore-pending flags clear.Explanation
The checker snapshots q at save time and performs the required one-cycle-later comparison only after a valid shutdown and restore sequence.
02
Requirements (4)
- Reset clears saved_valid, off_seen, and restore_pending. save is legal only while power_on=1 with all three clear and wr_en=0; it captures q and sets saved_valid. Any other save fails and changes no reference state.
- On the first sampled power_on=0 while off_seen=0, require saved_valid and set off_seen. On every off edge require q=0 and save=restore=wr_en=0.
- restore is legal only with power_on, saved_valid, off_seen, and no restore_pending. It sets restore_pending; on the next edge q must equal the saved value, then clear all three flags. Any other restore fails and preserves state.
- wr_en is legal only while power_on=1 before a save and before shutdown. A write after save, a save after shutdown, or a power-off transition without a saved value must assert-fail.