DescriptionQ781
Q781DesignBroadcomASIC interview problem
Ethernet low-power idle entry timer
TechniquesDesignLow powerPower sequencingEthernettimer
DifficultyMedium
TopicLow Power
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A port may request low-power idle after sixteen consecutive idle cycles and must cancel immediately when traffic returns. Write synthesizable SystemVerilog for the timer and request.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic tx_active, lpi_ack;
output logic lpi_req;Example input and output
Use this case to check your interpretationInput
tx_active remains 0 for sixteen consecutive rising edges after reset and lpi_ack remains 0.Output
lpi_req is 0 through the fifteenth edge and becomes 1 on the sixteenth edge.Explanation
The saturating counter records only consecutive idle edges and asserts the sticky request exactly at the threshold.
02
Requirements (4)
- Count consecutive rising edges with tx_active=0; any edge with tx_active=1 clears the count and lpi_req.
- Assert lpi_req immediately after the sixteenth consecutive idle edge and hold it until a valid acknowledgement or returning traffic.
- Honor lpi_ack only when lpi_req was already high and tx_active=0; otherwise ignore it and keep counting. If tx_active and lpi_ack coincide, traffic cancellation has priority.
- Synchronous active-low reset clears the counter and request; saturate the counter rather than wrapping.