DescriptionQ250
Q250DVASIC interview problem
Assert bounded eventual completion
TechniquesSVALivenessBounded latency
DifficultyMedium
TopicTemporal Checks
LanguageSystemVerilog
Requirements3 checkpoints
01
Problem
Write an assertion stating that every start must be followed by done within 1 through N cycles.
Example input and output
Use this case to check your interpretationInput
N=3; start at cycle2 and done at cycle5; separately try done in the same start cycleOutput
latency-3 completion passes; same-cycle completion fails the 1..3 consequentExplanation
The reset-disabled property admits only the first through third later sampled edges unless the protocol explicitly changes that bound.
02
Requirements (3)
- Sample on the positive clock edge.
- Disable the property during active-low reset.
- Do not allow same-cycle done unless the specification says so.