DescriptionQ293
Q293DVDesignASIC interview problem
Assert an integer square-root pipeline
TechniquesDVSVALatencyArithmeticBackpressure
DifficultyEasy
TopicTemporal Checks
LanguageSystemVerilog
Requirements5 checkpoints
01
Problem
Check a 32-bit floor-square-root block with fixed 16-cycle latency, one outstanding request, and a backpressured response. Verify both protocol timing and the arithmetic result.
Example input and output
Use this case to check your interpretationInput
accept radicand=27 at cycle0; response first asserts at cycle16 with root=5,remainder=2 and stalls until cycle18Output
fixed latency PASS; arithmetic PASS; root/remainder/valid stable through acceptance at cycle18Explanation
Five squared is 25 <= 27, six squared is 36 > 27, and remainder 27-25 is two; ready does not alter assertion latency.
02
Requirements (5)
- Associate each accepted radicand with the response that first asserts exactly LATENCY cycles later, regardless of rsp_ready.
- Check root squared is at most the radicand and the next root squared is greater, using widened products that represent 65536 squared.
- Check remainder equals radicand minus root squared on every accepted response.
- Hold rsp_valid, root, and remainder stable throughout response stalls.
- Cancel pending latency obligations on reset and cover boundary, perfect-square, near-square, and stalled cases.