Hardware interview practice
Assert bounded eventual completion
Write an assertion stating that every start must be followed by done within 1 through N cycles.
Reviewed example
Work through one case
Input
N=3; start at cycle2 and done at cycle5; separately try done in the same start cycleExpected output
latency-3 completion passes; same-cycle completion fails the 1..3 consequentThe reset-disabled property admits only the first through third later sampled edges unless the protocol explicitly changes that bound.
What to cover
Requirements
- Sample on the positive clock edge.
- Disable the property during active-low reset.
- Do not allow same-cycle done unless the specification says so.