1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ221

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Q221DesignMetaASIC interview problem

Closed-loop pulse synchronizer

TechniquesDesignCDCHandshakeToggleBackpressure

DifficultyMedium

TopicClock Domain Crossing

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A one-cycle command pulse must cross unrelated clocks without loss, and the source may wait while one command is in flight. Implement a toggle-and-acknowledge synchronizer with source busy.

Starting declarationSystemVerilog

input logic src_clk, src_rst_n, src_pulse;
output logic src_busy;
input logic dst_clk, dst_rst_n;
output logic dst_pulse;

Example input and output

Use this case to check your interpretation

Input

One src_pulse while src_busy=0; destination clocks at an unrelated rate

Output

Exactly one dst_pulse; src_busy clears only after acknowledgement returns

Explanation

The toggle persists across arbitrary phase alignment, and busy prevents a second event from overwriting it.

Requirements (4)

When src_pulse is sampled while src_busy is 0, toggle a source request bit; ignore or flag any src_pulse sampled while busy is 1.
Synchronize the request through two destination flops and emit dst_pulse for exactly one destination cycle when the synchronized toggle changes.
Return the observed toggle through a two-flop acknowledgement synchronizer; src_busy is 1 while request and synchronized acknowledgement differ.
Both active-low resets are asserted together for at least two cycles of both clocks and initialize request, acknowledgement, history, busy, and dst_pulse to zero.