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DescriptionQ148
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Q148DVASIC interview problem

Procedural stall-stability checker

TechniquesHandshakeProtocolChecker
DifficultyMedium
TopicTemporal Checks
LanguageSystemVerilog
Requirements3 checkpoints
01

Problem

At each clock, report an error when the previous cycle was stalled and current valid drops or the payload changes.

Example input and output

Use this case to check your interpretation
Input
previous cycle: valid=1, ready=0, payload=0xA4; current valid=1, payload=0xA5
Output
report a protocol error, then save the current handshake and payload for the next check
Explanation

The prior stalled cycle owns the stability obligation. A four-state comparison catches the change before the saved sample is updated.

02

Requirements (3)

  • Track the previous valid, ready, and payload values.
  • Use four-state comparison.
  • Check before updating the saved sample.