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Hardware interview practice

Procedural stall-stability checker

MediumTemporal ChecksSystemVerilog

At each clock, report an error when the previous cycle was stalled and current valid drops or the payload changes.

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Reviewed example

Work through one case

Input
previous cycle: valid=1, ready=0, payload=0xA4; current valid=1, payload=0xA5
Expected output
report a protocol error, then save the current handshake and payload for the next check

The prior stalled cycle owns the stability obligation. A four-state comparison catches the change before the saved sample is updated.

What to cover

Requirements

  1. Track the previous valid, ready, and payload values.
  2. Use four-state comparison.
  3. Check before updating the saved sample.
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Temporal ChecksCheck hold while stalled→FSMsControl a request/acknowledge handshake→
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