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DescriptionQ005

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Q005DesignDVASIC interview problem

Control a request/acknowledge handshake

TechniquesHandshakeMoore FSMProtocolResponder BFM

DifficultyMedium

TopicFSMs

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design a four-phase controller that accepts start while idle, holds req until ack, drops req, waits for ack to return low, and emits a one-cycle done pulse when ack is sampled. Write a responder bus functional model (BFM) with a configurable delay.

Three-state request-acknowledge controller beside a four-phase waveform for request, acknowledge, and one-cycle done. — Use the state flow and sampled waveform together to define when request holds and when done pulses.

Example input and output

Use this case to check your interpretation

Input

cycle 0: req=0, ack=0
cycle 1: req=1, ack=0
cycle 2: req=1, ack=1
cycle 3: req=0, ack=1
cycle 4: req=0, ack=0

Output

state: IDLE -> WAIT_ACK -> WAIT_REQ_LOW -> IDLE
done pulses once at cycle 2

Explanation

The controller holds the request phase until acknowledge and does not accept a second transaction until both sides return low.

Requirements (4)

Ignore additional start pulses while a transaction is active.
Keep req asserted continuously until ack is sampled.
Pulse done only for the req-and-ack handshake and do not return to idle until ack is low.
Initialize ack low and drive it for exactly one sampled cycle in the BFM.