DescriptionQ131
Q131DesignAppleASIC interview problem
Calculate a falling-to-rising half-cycle setup path
TechniquesDesignSTATimingCalculateA
DifficultyMedium
TopicTiming and STA
LanguageSystemVerilog
Format4 choices
01
Problem
A 2.00 ns clock launches data on its falling edge at time 0 and captures on the next rising edge 1.00 ns later. Clock-to-Q is 0.10 ns, maximum combinational delay is 0.65 ns, setup is 0.10 ns, and positive capture skew is 0.05 ns. Ignoring uncertainty, what is the setup slack?
02