DescriptionQ1077
Q1077DVAppleASIC interview problem
Constrain a balanced six-request descriptor set
TechniquesSystemVerilog & UVMSystemVerilog / UVMconstrain a balanced six-request descriptor set
DifficultyMedium
TopicSystemVerilog & UVM
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A block-level test needs six legal requests spread evenly across three command kinds. Write the SystemVerilog constraints for the request-set class.
Class declarationSystemVerilog
class req_set;
rand bit [15:0] addr[6];
rand bit [1:0] kind[6];
constraint legal_c;
endclassExample input and output
Use this case to check your interpretationInput
kind={0,1,2,0,1,2}, addr={16'h1004,16'h1008,16'h1040,16'h100C,16'h1010,16'h1080}.Output
The descriptor set is legal.Explanation
Each kind occurs twice without adjacent repetition, all addresses are distinct aligned words in range, and the two kind-2 addresses are 64-byte aligned.
02
Requirements (4)
- Every addr is word aligned and lies in the inclusive range 16'h1000 through 16'h10FC; all six addresses are different.
- Every kind is 0, 1, or 2, and exactly two array entries have each of the three kind values.
- Adjacent entries must have different kind values.
- Every entry with kind=2 must have a 64-byte-aligned address; do not enforce 64-byte alignment on kind 0 or 1.