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Hardware interview practice

Constrain a balanced six-request descriptor set

MediumSystemVerilog & UVMSystemVerilog

A block-level test needs six legal requests spread evenly across three command kinds. Write the SystemVerilog constraints for the request-set class.

Starting point

Question code

class req_set;
rand bit [15:0] addr[6];
rand bit [1:0] kind[6];
constraint legal_c;
endclass
Reviewed example

Work through one case

Input
kind={0,1,2,0,1,2}, addr={16'h1004,16'h1008,16'h1040,16'h100C,16'h1010,16'h1080}.
Expected output
The descriptor set is legal.

Each kind occurs twice without adjacent repetition, all addresses are distinct aligned words in range, and the two kind-2 addresses are 64-byte aligned.

What to cover

Requirements

  1. Every addr is word aligned and lies in the inclusive range 16'h1000 through 16'h10FC; all six addresses are different.
  2. Every kind is 0, 1, or 2, and exactly two array entries have each of the three kind values.
  3. Adjacent entries must have different kind values.
  4. Every entry with kind=2 must have a 64-byte-aligned address; do not enforce 64-byte alignment on kind 0 or 1.
Continue practicing
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