DescriptionQ068
Q068DVIntelASIC interview problem
UVM monitor for a framed byte stream
TechniquesSystemVerilog & UVMSystemVerilog / UVMuvm monitor for a framed byte stream
DifficultyMedium
TopicSystemVerilog & UVM
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A byte interface marks the first and last byte of each accepted packet. Write the core SystemVerilog/UVM monitor code that publishes complete packets.
Starting declarationSystemVerilog
input logic clk, rst_n;
input logic valid, ready, sop, eop;
input logic [7:0] data;
uvm_analysis_port #(packet_item) ap;Example input and output
Use this case to check your interpretationInput
Accepted beats are 8'h11 with sop=1, then 8'h22, then 8'h33 with eop=1.Output
Publish exactly one packet_item containing bytes {11,22,33}.Explanation
The SOP beat creates the item, each valid-ready handshake appends one byte, and the EOP handshake publishes and clears the completed packet.
02
Requirements (4)
- Sample a byte only on a rising edge where valid && ready is true; while valid&&!ready, require valid, sop, eop, and data to stay stable and accept nothing.
- Start a new item only on an accepted beat with sop=1, append every accepted byte, and publish on the accepted beat with eop=1.
- An accepted byte before SOP, or a second SOP before EOP, reports uvm_error, discards the partial item and offending beat, and returns to IDLE; the offending beat is not reused.
- When rst_n is 0, discard any partial item and publish nothing.