1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ1060

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Q1060DesignASIC interview problem

Choose one-hot or binary FSM encoding

TechniquesOne-hotBinary encodingFPGATiming

DifficultyMedium

TopicFSMs

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A 12-state high-performance field-programmable gate array (FPGA) controller can use four binary state bits or twelve one-hot bits. Choose an encoding, implement a one-hot state ring, and explain the timing and area tradeoffs rather than judging only flip-flop count.

Example input and output

Use this case to check your interpretation

Input

12-bit one-hot state=12'b0000_0000_0001; step=1; then inject illegal state=12'b0000_0000_0011

Output

normal step produces 12'b0000_0000_0010; illegal state asserts error and recovers to SAFE 12'b0000_0000_0001 on the next edge

Explanation

One-hot uses more flops than four-bit binary but can reduce LUT decode depth; illegal zero/multi-hot states take the explicit safe default.

Requirements (4)

Use exactly one state bit in normal operation and provide a safe default recovery state.
Advance one state per asserted step and otherwise hold state.
Explain why one-hot can reduce decode depth and fan-in on lookup-table (LUT) based fabrics.
Acknowledge that synthesis results, routing, power, and device architecture can change the best choice.