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DescriptionQ1051
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Q1051ArchIntelASIC interview problem

Choose the CXL protocol for device memory

TechniquesArchMicroarchitectureInterconnectChoosememory
DifficultyEasy
TopicComputer Architecture
LanguageSystemVerilog
Format4 choices
01

Problem

A host processor needs load/store access to private memory attached to an accelerator. Device management still uses the mandatory I/O path. Which CXL protocol carries the host's memory reads and writes to the accelerator's private memory?

02

Answer choices (4)