Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Choose the CXL protocol for device memory

Hardware interview practice

Choose the CXL protocol for device memory

EasyComputer ArchitectureSystemVerilog

A host processor needs load/store access to private memory attached to an accelerator. Device management still uses the mandatory I/O path. Which CXL protocol carries the host's memory reads and writes to the accelerator's private memory?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. CXL.mem
  2. B. CXL.io only
  3. C. CXL.cache
  4. D. PCIe Precision Time Measurement
Continue practicing

Related questions

Computer ArchitectureForward bytes from a small pending-write queue→Computer ArchitectureMatch hit-under-miss responses by transaction ID→Computer ArchitecturePlace a dense neural-network kernel→
asic.fyi · Learn silicon end to end.info@asic.fyi