DescriptionQ914
Q914ArchMicronASIC interview problem
Forward bytes from a small pending-write queue
TechniquesArchMicroarchitectureInterconnectForwardBytes
DifficultyMedium
TopicComputer Architecture
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A memory controller allows up to four pending masked writes. A read must see the newest pending byte for each lane before falling back to memory data. Implement the SystemVerilog reference model for enqueue, commit, and read prediction.
Class declarationSystemVerilog
class writeq_ref;
function bit enqueue(bit [15:0] addr, bit [31:0] data, bit [3:0] mask);
function bit commit();
function bit [31:0] predict_read(bit [15:0] addr, bit [31:0] mem_data);
endclassExample input and output
Use this case to check your interpretationInput
enqueue(0x100, 0xAABBCCDD, 4'b0011), then predict_read(0x100, 0x11223344).Output
predict_read returns 32'h1122CCDD.Explanation
The newest pending write forwards only masked byte lanes 0 and 1; lanes 2 and 3 remain from memory data.
02
Requirements (4)
- Construction starts with an empty queue. enqueue appends a write if fewer than four entries exist and mask is nonzero; return 1 on append, otherwise return 0 with the queue unchanged.
- commit removes the oldest entry and returns 1, or returns 0 without change when the queue is empty.
- predict_read starts with mem_data and, for each byte lane, uses the newest queued write at the exact same word address whose mask includes that lane.
- All addresses are byte addresses and must be four-byte aligned; an unaligned enqueue returns 0, while an unaligned predict_read returns 32'h0000_0000 and changes no queue state.