1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ1024

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Q1024DesignArchMicronASIC interview problem

Encode the highest active request and its one-hot form

TechniquesRTL DesignRTL / Microarchitectureencode the highest active request and its one-hot form

DifficultyEasy

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Eight repair sources share one reporting port. The highest-numbered active source has priority. Implement the combinational SystemVerilog priority encoder.

Starting declarationSystemVerilog

input logic [7:0] req;
output logic valid;
output logic [2:0] index;
output logic [7:0] onehot;

Example input and output

Use this case to check your interpretation

Input

req=8'b0010_1000.

Output

valid=1, index=5, onehot=8'b0010_0000.

Explanation

Request bits 5 and 3 are set; the highest-numbered request wins, and onehot contains only that winning bit.

Requirements (4)

When req is zero, drive valid=0, index=0, and onehot=0.
Otherwise valid=1 and index is the highest-numbered set bit in req.
When valid=1, onehot has exactly bit index set; lower-priority request bits do not appear in onehot.
Use complete combinational assignments with no latch; inputs are restricted to known zero and one values.