Skip to question
asic.fyi

Hardware interview practice

Encode the highest active request and its one-hot form

EasyRTL DesignSystemVerilog

Eight repair sources share one reporting port. The highest-numbered active source has priority. Implement the combinational SystemVerilog priority encoder.

Starting point

Question code

input logic [7:0] req;
output logic valid;
output logic [2:0] index;
output logic [7:0] onehot;
Reviewed example

Work through one case

Input
req=8'b0010_1000.
Expected output
valid=1, index=5, onehot=8'b0010_0000.

Request bits 5 and 3 are set; the highest-numbered request wins, and onehot contains only that winning bit.

What to cover

Requirements

  1. When req is zero, drive valid=0, index=0, and onehot=0.
  2. Otherwise valid=1 and index is the highest-numbered set bit in req.
  3. When valid=1, onehot has exactly bit index set; lower-priority request bits do not appear in onehot.
  4. Use complete combinational assignments with no latch; inputs are restricted to known zero and one values.
Continue practicing
RTL DesignEnabled modulo-five counterRTL DesignAccumulate a four-lane signed dot productRTL DesignXNOR from one 2-to-1 mux