Chapter 4 of 8 · Computer Architecture

Performance calculations

Work the quantitative problems with explicit hit-rate denominators, timing assumptions, units, and reproducible intermediate steps.

Change the memory latency Practice questions

Worked problems

Carry the probability through the hierarchy.

State the timing convention, convert percentages to probabilities, and multiply a penalty only by the fraction of instructions or accesses that actually pay it.

AMAT calculator

Price every miss at the level where it occurs.

Average latency

L1 hit timensL1 hit rate%L2 hit timensL2 hit rate after L1 miss%DRAM timens

AMAT = tL1 + mL1 × (tL2 + mL2 × tDRAM)

2 + 0.1 × (10 + 0.2 × 60)

4.2 ns

AMAT is 4.2 ns. L1 contributes 2 ns, L2 contributes 1 ns, and DRAM contributes 1.2 ns. L1 lookup is the largest contribution.

Pipeline CPI and MIPS

CPI = 1 + 0.25(0.20)(3) + 0.20(0.30)(1)

Branch misses add 0.15 CPI. Load-use stalls add 0.06 CPI.

CPI = 1.21MIPS = 2,500 MHz / 1.21 = 2,066.12

Three-level AMAT tradeoff

2 + 0.10(10 + 0.20 × 60) = 4.2 ns

With the proposed slower but higher-hit L2:

2 + 0.10(12 + 0.05 × 60) = 3.5 nsThe proposal improves AMAT by 0.7 ns, or 16.7%.

1 MiB, 8-way, 64-byte PIPT tag array

lines = 2²⁰ / 2⁶ = 2¹⁴
sets = 2¹⁴ / 2³ = 2¹¹
offset = 6 bits · index = 11 bits

For the source's implied 34-bit physical address, tag = 34 − 11 − 6 = 17 bits. Including one valid bit per line:

(17 + 1) × 2¹⁴ = 294,912 bits288 Kibit = 36 KiB

Write-back L1, write-through L2 CPI

memory-op fraction = 0.20 + 0.10 = 0.30expected data time = 0.30 × [2 + 0.10(15 + 0.20×70 + 0.40×15)] = 1.65 ns/instruction

The prompt supplies nanoseconds but no processor clock period, so a unique CPI cannot be derived. For clock period T in ns:

CPI = 1 + 1.65 / TAt T = 1 ns, CPI = 2.65. If the base pipeline already includes the 2 ns L1 hit, count only miss overhead: CPI = 1 + 1.05/T, or 2.05 at T = 1 ns.

Four-level page-table EMAT

The translated 48-bit virtual address splits into four nine-bit indexes and a 12-bit offset. A 40-bit physical address has a 28-bit PPN plus that offset. Eight-byte PTEs make each 512-entry page-table level exactly 4 KiB.

translation = 1 + 0.01(4 × 100) = 5 cyclesdata access = 1 + 0.05(100) = 6 cycles

A TLB miss pays four uncached PTE reads. The subsequent L1 lookup still occurs, and an L1 miss pays one DRAM access. This exercise uses the source's serial TLB-then-cache timing model; a VIPT implementation may overlap part of those hit paths.

EMAT = 5 + 6 = 11 cycles

Put it into practice

Explain the mechanism. Test your reasoning.

Use the experiment above to support your answer, then apply the idea in the question bank.

Browse architecture questions

Continue the learning path

Next: Parallelism & speedup

Separate theoretical opportunity from realized throughput, quantify the serial ceiling, and compare deeper, wider, and multicore designs with explicit assumptions.