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Physical Design Engineer Interview Questions

Practice the complete Physical Design Engineer collection

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Showing 26 of 26All questions visible
  1. Q080Physical DesignOrder an RTL-to-GDS flowPhysical design · RTL-to-GDSEasy
  2. Q1041Physical DesignMatch a physical-signoff failure to its fixDesign · Physical designMediumP
  3. Q281Physical DesignFloorplan a four-bank SRAM subsystemDesign · SRAMMediumP
  4. Q645Physical DesignFirst response to a macro-channel hotspotDesign · Physical designEasyP
  5. Q347Physical DesignRelieve localized routing congestionDesign · Physical DesignEasyP
  6. Q321Physical DesignTrade speed for leakage with multi-Vt cellsDesign · Physical DesignEasyP
  7. Q537Physical DesignChoose a localized IR-drop repairDesign · Physical designMediumP
  8. Q480Physical DesignMinimum parallel straps for IR and EM limitsDesign · Power integrityHardP
  9. Q1102Physical DesignScale distributed-wire delay with lengthDesign · Physical DesignEasyP
  10. Q1121Physical DesignPredict opposite-direction crosstalk delayDesign · Physical DesignEasyP
  11. Q806Physical DesignExplain the routing antenna effectDesign · Physical DesignEasyP
  12. Q212TimingSeparate skew, jitter, latency, and uncertaintyDesign · STAEasyP
  13. Q593Design VerificationCompare static timing analysis with timing simulationDV · DesignEasyP
  14. Q612TimingCalculate setup and hold slack with clock latencyDesign · STAMediumP
  15. Q114TimingClassify timing-path startpoints and endpointsDesign · STAEasy
  16. Q1149Clock and Reset DomainsReview and scope false-path candidatesDesign · CDCMediumP
  17. Q333Static Timing AnalysisDistinguish clock-group relationship typesDesign · TimingEasyP
  18. Q431Static Timing AnalysisChoose first-order setup and hold fixesDesign · TimingEasyP
  19. Q663Static Timing AnalysisFind fmax for a half-cycle timing pathDesign · TimingMediumP
  20. Q739Static Timing AnalysisUse different setup and hold uncertaintyDesign · TimingMediumP
  21. Q847Static Timing AnalysisExplain CRPR in a timing reportDesign · TimingEasyP
  22. Q1060Static Timing AnalysisExplain OCV derates and temperatureDesign · TimingMediumP
  23. Q1075Timing and STAPair setup and hold multicycle constraintsDesign · STAMediumP
  24. Q965Timing and STAConstrain a source-synchronous read strobeDesign · STAMediumP
  25. Q267Timing and STAChoose coupled setup and hold ECOsDesign · STAHardP
  26. Q1008Timing and STAMinimum cells for two-corner closureDesign · STAHardP
Role study path

Physical Design Engineer interview preparation

Prepare for physical design engineer interviews with curated questions on RTL-to-GDS, floorplanning, placement, routing, STA, clocking, IR drop, and signoff.

Follow the RTL-to-GDS flow through floorplanning, routing, clock and timing constraints, signal integrity, power integrity, physical ECOs, and multi-corner signoff decisions.